diff options
| author | nyamatongwe <devnull@localhost> | 2004-10-16 00:41:27 +0000 |
|---|---|---|
| committer | nyamatongwe <devnull@localhost> | 2004-10-16 00:41:27 +0000 |
| commit | df74730c0929fdf64d8bada8ad3101ff30e1ffa1 (patch) | |
| tree | 1dbc8b37f75d451bbb8bfeb8b9865c3056017dc1 | |
| parent | f684ccb3c524698d31423ba7d04117e2cb8712a2 (diff) | |
| download | scintilla-mirror-df74730c0929fdf64d8bada8ad3101ff30e1ffa1.tar.gz | |
VHDL lexer contributed by Phil Reid.
| -rw-r--r-- | win32/makefile | 2 | ||||
| -rw-r--r-- | win32/scintilla.mak | 3 | ||||
| -rw-r--r-- | win32/scintilla_vc6.mak | 3 |
3 files changed, 7 insertions, 1 deletions
diff --git a/win32/makefile b/win32/makefile index 908a0e56f..473ffe0f2 100644 --- a/win32/makefile +++ b/win32/makefile @@ -57,7 +57,7 @@ LexErlang.o LexEScript.o LexForth.o LexFortran.o LexGui4Cli.o LexHTML.o \ LexKix.o LexLisp.o LexLout.o LexLua.o LexMatlab.o LexMetapost.o LexMMIXAL.o \ LexMPT.o LexMSSQL.o LexNsis.o LexOthers.o LexPascal.o LexPB.o LexPerl.o \ LexPOV.o LexPS.o LexPython.o LexRuby.o LexScriptol.o LexSpecman.o LexSQL.o \ -LexTeX.o LexVB.o LexVerilog.o LexYAML.o +LexTeX.o LexVB.o LexVerilog.o LexVHDL.o LexYAML.o #--Autogenerated -- end of automatically generated section SOBJS = ScintillaWin.o ScintillaBase.o Editor.o Document.o \ diff --git a/win32/scintilla.mak b/win32/scintilla.mak index 7c0165881..99d978e8a 100644 --- a/win32/scintilla.mak +++ b/win32/scintilla.mak @@ -154,6 +154,7 @@ LEXOBJS=\ $(DIR_O)\LexTeX.obj \ $(DIR_O)\LexVB.obj \ $(DIR_O)\LexVerilog.obj \ + $(DIR_O)\LexVHDL.obj \ $(DIR_O)\LexYAML.obj \ #--Autogenerated -- end of automatically generated section @@ -354,6 +355,8 @@ $(DIR_O)\LexVB.obj: ..\src\LexVB.cxx $(LEX_HEADERS) $(DIR_O)\LexVerilog.obj: ..\src\LexVerilog.cxx $(LEX_HEADERS) +$(DIR_O)\LexVHDL.obj: ..\src\LexVHDL.cxx $(LEX_HEADERS) + $(DIR_O)\LexYAML.obj: ..\src\LexYAML.cxx $(LEX_HEADERS) diff --git a/win32/scintilla_vc6.mak b/win32/scintilla_vc6.mak index b0ba950b4..29d6a493e 100644 --- a/win32/scintilla_vc6.mak +++ b/win32/scintilla_vc6.mak @@ -156,6 +156,7 @@ LEXOBJS=\ $(DIR_O)\LexTeX.obj \ $(DIR_O)\LexVB.obj \ $(DIR_O)\LexVerilog.obj \ + $(DIR_O)\LexVHDL.obj \ $(DIR_O)\LexYAML.obj \ #--Autogenerated -- end of automatically generated section @@ -356,6 +357,8 @@ $(DIR_O)\LexVB.obj: ..\src\LexVB.cxx $(LEX_HEADERS) $(DIR_O)\LexVerilog.obj: ..\src\LexVerilog.cxx $(LEX_HEADERS) +$(DIR_O)\LexVHDL.obj: ..\src\LexVHDL.cxx $(LEX_HEADERS) + $(DIR_O)\LexYAML.obj: ..\src\LexYAML.cxx $(LEX_HEADERS) |