Fixed warnings.

1 files changed, 20 insertions, 20 deletions

diff --git a/src/LexVHDL.cxx b/src/LexVHDL.cxx
index bd9a0a8ee..c0733ab82 100644
--- a/src/LexVHDL.cxx
+++ b/src/LexVHDL.cxx
@@ -1,9 +1,9 @@
 // Scintilla source code edit control
 /** @file LexVHDL.cxx
  ** Lexer for VHDL
- ** Written by Phil Reid, 
+ ** Written by Phil Reid,
  ** Based on:
- **  - The Verilog Lexer by Avi Yegudin 
+ **  - The Verilog Lexer by Avi Yegudin
  **  - The Fortran Lexer by Chuan-jian Shen
  **  - The C++ lexer by Neil Hodgson
  **/
@@ -126,7 +126,7 @@ static void ColouriseVHDLDoc(
         sc.SetState(SCE_VHDL_IDENTIFIER);
       } else if (sc.Match('-', '-')) {
         sc.SetState(SCE_VHDL_COMMENT);
-        sc.Forward(); 
+        sc.Forward();
       } else if (sc.Match('-', '-')) {
         if (sc.Match("--!"))  // Nice to have a different comment style
           sc.SetState(SCE_VHDL_COMMENTLINEBANG);
@@ -161,7 +161,7 @@ static bool IsCommentLine(int line, Accessor &styler) {
 static void FoldNoBoxVHDLDoc(
   unsigned int startPos,
   int length,
-  int initStyle,
+  int,
   Accessor &styler)
 {
   // Decided it would be smarter to have the lexer have all keywords included. Therefore I
@@ -268,12 +268,12 @@ static void FoldNoBoxVHDLDoc(
     styleNext       = styler.StyleAt(i + 1);
     bool atEOL      = (ch == '\r' && chNext != '\n') || (ch == '\n');
 
-		if (foldComment && atEOL && IsCommentLine(lineCurrent, styler)) 
+		if (foldComment && atEOL && IsCommentLine(lineCurrent, styler))
     {
       if(!IsCommentLine(lineCurrent-1, styler) && IsCommentLine(lineCurrent+1, styler))
       {
         levelNext++;
-      } 
+      }
       else if(IsCommentLine(lineCurrent-1, styler) && !IsCommentLine(lineCurrent+1, styler))
       {
         levelNext--;
@@ -379,7 +379,7 @@ static void FoldNoBoxVHDLDoc(
             ((strcmp(s, "begin") == 0) && (strcmp(prevWord, "function") == 0)) ||
             ((strcmp(s, "begin") == 0) && (strcmp(prevWord, "procedure") == 0)))
           {
-            levelMinCurrentBegin = levelNext - 1;  
+            levelMinCurrentBegin = levelNext - 1;
           }
           //Platform::DebugPrintf("Line[%04d] Prev[%20s] Cur[%20s] Level[%x]\n", lineCurrent+1, prevWord, s, levelCurrent);
           strcpy(prevWord, s);
@@ -443,34 +443,34 @@ LexerModule lmVHDL(SCLEX_VHDL, ColouriseVHDLDoc, "vhdl", FoldVHDLDoc, VHDLWordLi
 
 
 // Keyword:
-//    access after alias all architecture array assert attribute begin block body buffer bus case component 
-//    configuration constant disconnect downto else elsif end entity exit file for function generate generic 
-//    group guarded if impure in inertial inout is label library linkage literal loop map new next null of 
-//    on open others out package port postponed procedure process pure range record register reject report 
-//    return select severity shared signal subtype then to transport type unaffected units until use variable 
+//    access after alias all architecture array assert attribute begin block body buffer bus case component
+//    configuration constant disconnect downto else elsif end entity exit file for function generate generic
+//    group guarded if impure in inertial inout is label library linkage literal loop map new next null of
+//    on open others out package port postponed procedure process pure range record register reject report
+//    return select severity shared signal subtype then to transport type unaffected units until use variable
 //    wait when while with
 //
 // Operators:
 //    abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
 //
 // Attributes:
-//    left right low high ascending image value pos val succ pred leftof rightof base range reverse_range 
-//    length delayed stable quiet transaction event active last_event last_active last_value driving 
+//    left right low high ascending image value pos val succ pred leftof rightof base range reverse_range
+//    length delayed stable quiet transaction event active last_event last_active last_value driving
 //    driving_value simple_name path_name instance_name
 //
 // Std Functions:
-//    now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector 
-//    to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left 
+//    now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector
+//    to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left
 //    rotate_right resize to_integer to_unsigned to_signed std_match to_01
 //
 // Std Packages:
-//    std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed 
-//    std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives 
+//    std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed
+//    std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives
 //    vital_timing
 //
 // Std Types:
-//    boolean bit character severity_level integer real time delay_length natural positive string bit_vector 
-//    file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic 
+//    boolean bit character severity_level integer real time delay_length natural positive string bit_vector
+//    file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic
 //    std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
 //