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-rw-r--r--lexers/LexVHDL.cxx3
1 files changed, 2 insertions, 1 deletions
diff --git a/lexers/LexVHDL.cxx b/lexers/LexVHDL.cxx
index 86f93f4e7..5fa428bce 100644
--- a/lexers/LexVHDL.cxx
+++ b/lexers/LexVHDL.cxx
@@ -216,7 +216,7 @@ static void FoldNoBoxVHDLDoc(
// don't check if the style for the keywords that I use to adjust the levels.
char words[] =
"architecture begin block case component else elsif end entity generate loop package process record then "
- "procedure function when units";
+ "procedure protected function when units";
WordList keywords;
keywords.Set(words);
@@ -381,6 +381,7 @@ static void FoldNoBoxVHDLDoc(
strcmp(s, "loop") == 0 ||
strcmp(s, "package") ==0 ||
strcmp(s, "process") == 0 ||
+ strcmp(s, "protected") == 0 ||
strcmp(s, "record") == 0 ||
strcmp(s, "then") == 0 ||
strcmp(s, "units") == 0)