From 9884db899009ee9a9a02b424ed98487c1abcd687 Mon Sep 17 00:00:00 2001
From: Neil Hodgson <nyamatongwe@gmail.com>
Date: Wed, 11 Mar 2015 10:59:10 +1100
Subject: Change log.

---
 doc/ScintillaHistory.html | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'doc/ScintillaHistory.html')

diff --git a/doc/ScintillaHistory.html b/doc/ScintillaHistory.html
index d7af49269..f2b2b2acf 100644
--- a/doc/ScintillaHistory.html
+++ b/doc/ScintillaHistory.html
@@ -483,6 +483,17 @@
     <h3>
        <a href="http://prdownloads.sourceforge.net/scintilla/scite354.zip?download">Release 3.5.4</a>
     </h3>
+    <ul>
+	<li>
+	Released 8 March 2015.
+	</li>
+	<li>
+	Verilog folder fixes bug with `end completing an `if* instead of `endif.
+	</li>
+    </ul>
+    <h3>
+       <a href="http://prdownloads.sourceforge.net/scintilla/scite354.zip?download">Release 3.5.4</a>
+    </h3>
     <ul>
 	<li>
 	Released 8 March 2015.
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