From fe85d455e4ee2edaf55ac42077e7d9642fb9688e Mon Sep 17 00:00:00 2001
From: Joe Mueller <devnull@localhost>
Date: Tue, 10 Mar 2015 15:14:14 -0700
Subject: fix problem where preprocessor fold code would incorrectly match
 `endcelldefine with `if

---
 lexers/LexVerilog.cxx | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'lexers')

diff --git a/lexers/LexVerilog.cxx b/lexers/LexVerilog.cxx
index 2a53a1846..1e45a06bc 100644
--- a/lexers/LexVerilog.cxx
+++ b/lexers/LexVerilog.cxx
@@ -853,7 +853,7 @@ void SCI_METHOD LexerVerilog::Fold(unsigned int startPos, int length, int initSt
 				}
 				if (styler.Match(j, "if")) {
 					levelNext++;
-				} else if (styler.Match(j, "end")) {
+				} else if (styler.Match(j, "endif")) {
 					levelNext--;
 				}
 			}
-- 
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