From 264a32988784bc42f44823af279bff3bb5b7ebbf Mon Sep 17 00:00:00 2001
From: nyamatongwe <unknown>
Date: Tue, 20 Jan 2004 10:39:33 +0000
Subject: Support from Avi Yegudin for Verilog.

---
 src/KeyWords.cxx | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/KeyWords.cxx b/src/KeyWords.cxx
index dc7035388..2ae4a2c99 100644
--- a/src/KeyWords.cxx
+++ b/src/KeyWords.cxx
@@ -182,6 +182,7 @@ int Scintilla_LinkLexers() {
 	LINK_LEXER(lmTeX);
 	LINK_LEXER(lmVB);
 	LINK_LEXER(lmVBScript);
+	LINK_LEXER(lmVerilog);
 	LINK_LEXER(lmYAML);
 
 //--Autogenerated -- end of automatically generated section
-- 
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