From 89fdad19d372aa9c8351c3693b835fd1a18ff01f Mon Sep 17 00:00:00 2001 From: ssteele Date: Mon, 16 Feb 2004 11:31:32 +0000 Subject: Added MSSQL and Verilog lexers. --- vcbuild/SciLexer.dsp | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'vcbuild') diff --git a/vcbuild/SciLexer.dsp b/vcbuild/SciLexer.dsp index 1015bd646..d32f82618 100644 --- a/vcbuild/SciLexer.dsp +++ b/vcbuild/SciLexer.dsp @@ -230,6 +230,10 @@ SOURCE=..\src\LexMPT.cxx # End Source File # Begin Source File +SOURCE=..\src\LexMSSQL.cxx +# End Source File +# Begin Source File + SOURCE=..\src\LexNsis.cxx # End Source File # Begin Source File @@ -282,6 +286,10 @@ SOURCE=..\src\LexVB.cxx # End Source File # Begin Source File +SOURCE=..\src\LexVerilog.cxx +# End Source File +# Begin Source File + SOURCE=..\src\LexYAML.cxx # End Source File # Begin Source File -- cgit v1.2.3