From 90bf78ccc9dac99db85fe79218ec2ecd4b86c990 Mon Sep 17 00:00:00 2001 From: nyamatongwe Date: Tue, 20 Jan 2004 10:39:33 +0000 Subject: Support from Avi Yegudin for Verilog. --- win32/scintilla.mak | 3 +++ 1 file changed, 3 insertions(+) (limited to 'win32/scintilla.mak') diff --git a/win32/scintilla.mak b/win32/scintilla.mak index 415c92f5a..df1ed1d8b 100644 --- a/win32/scintilla.mak +++ b/win32/scintilla.mak @@ -146,6 +146,7 @@ LEXOBJS=\ $(DIR_O)\LexSQL.obj \ $(DIR_O)\LexTeX.obj \ $(DIR_O)\LexVB.obj \ + $(DIR_O)\LexVerilog.obj \ $(DIR_O)\LexYAML.obj \ #--Autogenerated -- end of automatically generated section @@ -330,6 +331,8 @@ $(DIR_O)\LexTeX.obj: ..\src\LexTeX.cxx $(LEX_HEADERS) $(DIR_O)\LexVB.obj: ..\src\LexVB.cxx $(LEX_HEADERS) +$(DIR_O)\LexVerilog.obj: ..\src\LexVerilog.cxx $(LEX_HEADERS) + $(DIR_O)\LexYAML.obj: ..\src\LexYAML.cxx $(LEX_HEADERS) -- cgit v1.2.3