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!* AUTO-GENERATED FROM SCITE PROPERTY SET *!
@[lexer.test.vhdl]{
:EN*.vhdQ*"S -1 '
:EN*.vhdlQ*
}
@[lexer.set.vhdl]{
ESSETILEXERvhdl
0ESSETKEYWORDS
access after alias all architecture array assert attribute begin block body
buffer bus case component configuration constant disconnect downto else elsif end
entity exit file for function generate generic group guarded if impure in inertial
inout is label library linkage literal loop map new next null of on open others
out package port postponed procedure process pure range record register reject
report return select severity shared signal subtype then to transport type
unaffected units until use variable wait when while with
1ESSETKEYWORDS
abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
2ESSETKEYWORDS
left right low high ascending image value pos val succ pred leftof rightof
base range reverse_range length delayed stable quiet transaction event active
last_event last_active last_value driving driving_value simple_name path_name
instance_name
3ESSETKEYWORDS
now readline read writeline write endfile resolved to_bit to_bitvector
to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge
falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer
to_unsigned to_signed std_match to_01
4ESSETKEYWORDS
std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc
std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex
math_real vital_primitives vital_timing
5ESSETKEYWORDS
boolean bit character severity_level integer real time delay_length natural
positive string bit_vector file_open_kind file_open_status line text side width
std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned
signed
:M[color.comment],1M[color.set]
:M[color.number],3M[color.set]
:M[color.string],4M[color.set]
:M[color.keyword],8M[color.set]
}
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