Support from Avi Yegudin for Verilog.

8 files changed, 44 insertions, 2 deletions

diff --git a/gtk/makefile b/gtk/makefile
index 8e749f36e..9c010d8f8 100644
--- a/gtk/makefile
+++ b/gtk/makefile
@@ -63,7 +63,7 @@ LexCrontab.o LexCSS.o LexEiffel.o LexErlang.o LexEScript.o LexForth.o \
 LexFortran.o LexHTML.o LexLisp.o LexLout.o LexLua.o LexMatlab.o LexMetapost.o \
 LexMMIXAL.o LexMPT.o LexMSSQL.o LexNsis.o LexOthers.o LexPascal.o LexPB.o \
 LexPerl.o LexPOV.o LexPS.o LexPython.o LexRuby.o LexScriptol.o LexSQL.o \
-LexTeX.o LexVB.o LexYAML.o
+LexTeX.o LexVB.o LexVerilog.o LexYAML.o
 #--Autogenerated -- end of automatically generated section
 
 all: $(COMPLIB)
diff --git a/gtk/scintilla.mak b/gtk/scintilla.mak
index 12cbaed6d..504708ff1 100644
--- a/gtk/scintilla.mak
+++ b/gtk/scintilla.mak
@@ -157,6 +157,7 @@ LEXOBJS=\
 	$(DIR_O)\LexSQL.obj \
 	$(DIR_O)\LexTeX.obj \
 	$(DIR_O)\LexVB.obj \
+	$(DIR_O)\LexVerilog.obj \
 	$(DIR_O)\LexYAML.obj \
 
 #--Autogenerated -- end of automatically generated section
@@ -344,6 +345,8 @@ $(DIR_O)\LexTeX.obj: ..\src\LexTeX.cxx $(LEX_HEADERS)
 
 $(DIR_O)\LexVB.obj: ..\src\LexVB.cxx $(LEX_HEADERS)
 
+$(DIR_O)\LexVerilog.obj: ..\src\LexVerilog.cxx $(LEX_HEADERS)
+
 $(DIR_O)\LexYAML.obj: ..\src\LexYAML.cxx $(LEX_HEADERS)
 
 
diff --git a/include/SciLexer.h b/include/SciLexer.h
index 1960cead4..a93397adc 100644
--- a/include/SciLexer.h
+++ b/include/SciLexer.h
@@ -70,6 +70,7 @@
 #define SCLEX_ERLANG 53
 #define SCLEX_OCTAVE 54
 #define SCLEX_MSSQL 55
+#define SCLEX_VERILOG 56
 #define SCLEX_AUTOMATIC 1000
 #define SCE_P_DEFAULT 0
 #define SCE_P_COMMENTLINE 1
@@ -650,6 +651,20 @@
 #define SCE_MSSQL_SYSTABLE 11
 #define SCE_MSSQL_GLOBAL_VARIABLE 12
 #define SCE_MSSQL_FUNCTION 13
+#define SCE_V_DEFAULT 0
+#define SCE_V_COMMENT 1
+#define SCE_V_COMMENTLINE 2
+#define SCE_V_COMMENTLINEBANG 3
+#define SCE_V_NUMBER 4
+#define SCE_V_WORD 5
+#define SCE_V_STRING 6
+#define SCE_V_WORD2 7
+#define SCE_V_WORD3 8
+#define SCE_V_PREPROCESSOR 9
+#define SCE_V_OPERATOR 10
+#define SCE_V_IDENTIFIER 11
+#define SCE_V_STRINGEOL 12
+#define SCE_V_USER 19
 //--Autogenerated -- end of section automatically generated from Scintilla.iface
 
 #endif
diff --git a/include/Scintilla.iface b/include/Scintilla.iface
index 5688bd386..5ee7afd5f 100644
--- a/include/Scintilla.iface
+++ b/include/Scintilla.iface
@@ -1692,6 +1692,7 @@ val SCLEX_FORTH=52
 val SCLEX_ERLANG=53
 val SCLEX_OCTAVE=54
 val SCLEX_MSSQL=55
+val SCLEX_VERILOG=56
 
 # When a lexer specifies its language as SCLEX_AUTOMATIC it receives a
 # value assigned in sequence from SCLEX_AUTOMATIC+1.
@@ -2377,6 +2378,22 @@ val SCE_MSSQL_DATATYPE=10
 val SCE_MSSQL_SYSTABLE=11
 val SCE_MSSQL_GLOBAL_VARIABLE=12
 val SCE_MSSQL_FUNCTION=13
+# Lexical states for SCLEX_VERILOG
+lex Verilog=SCLEX_VERILOG SCE_V_
+val SCE_V_DEFAULT=0
+val SCE_V_COMMENT=1
+val SCE_V_COMMENTLINE=2
+val SCE_V_COMMENTLINEBANG=3
+val SCE_V_NUMBER=4
+val SCE_V_WORD=5
+val SCE_V_STRING=6
+val SCE_V_WORD2=7
+val SCE_V_WORD3=8
+val SCE_V_PREPROCESSOR=9
+val SCE_V_OPERATOR=10
+val SCE_V_IDENTIFIER=11
+val SCE_V_STRINGEOL=12
+val SCE_V_USER=19
 
 # Events
 
diff --git a/src/KeyWords.cxx b/src/KeyWords.cxx
index dc7035388..2ae4a2c99 100644
--- a/src/KeyWords.cxx
+++ b/src/KeyWords.cxx
@@ -182,6 +182,7 @@ int Scintilla_LinkLexers() {
 	LINK_LEXER(lmTeX);
 	LINK_LEXER(lmVB);
 	LINK_LEXER(lmVBScript);
+	LINK_LEXER(lmVerilog);
 	LINK_LEXER(lmYAML);
 
 //--Autogenerated -- end of automatically generated section
diff --git a/win32/makefile b/win32/makefile
index a4edc6613..effbb6bb6 100644
--- a/win32/makefile
+++ b/win32/makefile
@@ -55,7 +55,7 @@ LexCrontab.o LexCSS.o LexEiffel.o LexErlang.o LexEScript.o LexForth.o \
 LexFortran.o LexHTML.o LexLisp.o LexLout.o LexLua.o LexMatlab.o LexMetapost.o \
 LexMMIXAL.o LexMPT.o LexMSSQL.o LexNsis.o LexOthers.o LexPascal.o LexPB.o \
 LexPerl.o LexPOV.o LexPS.o LexPython.o LexRuby.o LexScriptol.o LexSQL.o \
-LexTeX.o LexVB.o LexYAML.o
+LexTeX.o LexVB.o LexVerilog.o LexYAML.o
 #--Autogenerated -- end of automatically generated section
 
 SOBJS	= ScintillaWin.o ScintillaBase.o Editor.o Document.o \
diff --git a/win32/scintilla.mak b/win32/scintilla.mak
index 415c92f5a..df1ed1d8b 100644
--- a/win32/scintilla.mak
+++ b/win32/scintilla.mak
@@ -146,6 +146,7 @@ LEXOBJS=\
 	$(DIR_O)\LexSQL.obj \
 	$(DIR_O)\LexTeX.obj \
 	$(DIR_O)\LexVB.obj \
+	$(DIR_O)\LexVerilog.obj \
 	$(DIR_O)\LexYAML.obj \
 
 #--Autogenerated -- end of automatically generated section
@@ -330,6 +331,8 @@ $(DIR_O)\LexTeX.obj: ..\src\LexTeX.cxx $(LEX_HEADERS)
 
 $(DIR_O)\LexVB.obj: ..\src\LexVB.cxx $(LEX_HEADERS)
 
+$(DIR_O)\LexVerilog.obj: ..\src\LexVerilog.cxx $(LEX_HEADERS)
+
 $(DIR_O)\LexYAML.obj: ..\src\LexYAML.cxx $(LEX_HEADERS)
 
 
diff --git a/win32/scintilla_vc6.mak b/win32/scintilla_vc6.mak
index 53ad2fd1d..176e089f6 100644
--- a/win32/scintilla_vc6.mak
+++ b/win32/scintilla_vc6.mak
@@ -148,6 +148,7 @@ LEXOBJS=\
 	$(DIR_O)\LexSQL.obj \
 	$(DIR_O)\LexTeX.obj \
 	$(DIR_O)\LexVB.obj \
+	$(DIR_O)\LexVerilog.obj \
 	$(DIR_O)\LexYAML.obj \
 
 #--Autogenerated -- end of automatically generated section
@@ -332,6 +333,8 @@ $(DIR_O)\LexTeX.obj: ..\src\LexTeX.cxx $(LEX_HEADERS)
 
 $(DIR_O)\LexVB.obj: ..\src\LexVB.cxx $(LEX_HEADERS)
 
+$(DIR_O)\LexVerilog.obj: ..\src\LexVerilog.cxx $(LEX_HEADERS)
+
 $(DIR_O)\LexYAML.obj: ..\src\LexYAML.cxx $(LEX_HEADERS)