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| author | ssteele <unknown> | 2004-02-16 11:31:32 +0000 |
|---|---|---|
| committer | ssteele <unknown> | 2004-02-16 11:31:32 +0000 |
| commit | 89fdad19d372aa9c8351c3693b835fd1a18ff01f (patch) | |
| tree | 19c877762224e497e30eefcde69bb24de8e35727 | |
| parent | e5d4fc19ec29a609071f6942424781d7a63e3819 (diff) | |
| download | scintilla-mirror-89fdad19d372aa9c8351c3693b835fd1a18ff01f.tar.gz | |
Added MSSQL and Verilog lexers.
| -rw-r--r-- | vcbuild/SciLexer.dsp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/vcbuild/SciLexer.dsp b/vcbuild/SciLexer.dsp index 1015bd646..d32f82618 100644 --- a/vcbuild/SciLexer.dsp +++ b/vcbuild/SciLexer.dsp @@ -230,6 +230,10 @@ SOURCE=..\src\LexMPT.cxx # End Source File # Begin Source File +SOURCE=..\src\LexMSSQL.cxx +# End Source File +# Begin Source File + SOURCE=..\src\LexNsis.cxx # End Source File # Begin Source File @@ -282,6 +286,10 @@ SOURCE=..\src\LexVB.cxx # End Source File # Begin Source File +SOURCE=..\src\LexVerilog.cxx +# End Source File +# Begin Source File + SOURCE=..\src\LexYAML.cxx # End Source File # Begin Source File |