VHDL lexer contributed by Phil Reid.

6 files changed, 40 insertions, 1 deletions

diff --git a/doc/ScintillaHistory.html b/doc/ScintillaHistory.html
index aa79a40df..1d1e52f0b 100644
--- a/doc/ScintillaHistory.html
+++ b/doc/ScintillaHistory.html
@@ -178,6 +178,7 @@
 	<li>Gene Barry</li>
 	<li>Niki Spahiev</li>
 	<li>Carsten Sperber</li>
+	<li>Phil Reid</li>
     </ul>
     <p>
        Images used in GTK+ version
diff --git a/gtk/makefile b/gtk/makefile
index cd07650a7..774e6730e 100644
--- a/gtk/makefile
+++ b/gtk/makefile
@@ -69,7 +69,7 @@ LexErlang.o LexEScript.o LexForth.o LexFortran.o LexGui4Cli.o LexHTML.o \
 LexKix.o LexLisp.o LexLout.o LexLua.o LexMatlab.o LexMetapost.o LexMMIXAL.o \
 LexMPT.o LexMSSQL.o LexNsis.o LexOthers.o LexPascal.o LexPB.o LexPerl.o \
 LexPOV.o LexPS.o LexPython.o LexRuby.o LexScriptol.o LexSpecman.o LexSQL.o \
-LexTeX.o LexVB.o LexVerilog.o LexYAML.o
+LexTeX.o LexVB.o LexVerilog.o LexVHDL.o LexYAML.o
 #--Autogenerated -- end of automatically generated section
 
 all: $(COMPLIB)
diff --git a/gtk/scintilla.mak b/gtk/scintilla.mak
index b11351e69..a1a536827 100644
--- a/gtk/scintilla.mak
+++ b/gtk/scintilla.mak
@@ -184,6 +184,7 @@ LEXOBJS=\
 	$(DIR_O)\LexTeX.obj \
 	$(DIR_O)\LexVB.obj \
 	$(DIR_O)\LexVerilog.obj \
+	$(DIR_O)\LexVHDL.obj \
 	$(DIR_O)\LexYAML.obj \
 
 #--Autogenerated -- end of automatically generated section
@@ -391,6 +392,8 @@ $(DIR_O)\LexVB.obj: ..\src\LexVB.cxx $(LEX_HEADERS)
 
 $(DIR_O)\LexVerilog.obj: ..\src\LexVerilog.cxx $(LEX_HEADERS)
 
+$(DIR_O)\LexVHDL.obj: ..\src\LexVHDL.cxx $(LEX_HEADERS)
+
 $(DIR_O)\LexYAML.obj: ..\src\LexYAML.cxx $(LEX_HEADERS)
 
 
diff --git a/include/SciLexer.h b/include/SciLexer.h
index 666ad09fe..ce50a7fab 100644
--- a/include/SciLexer.h
+++ b/include/SciLexer.h
@@ -78,6 +78,7 @@
 #define SCLEX_APDL 61
 #define SCLEX_BASH 62
 #define SCLEX_ASN1 63
+#define SCLEX_VHDL 64
 #define SCLEX_AUTOMATIC 1000
 #define SCE_P_DEFAULT 0
 #define SCE_P_COMMENTLINE 1
@@ -768,6 +769,21 @@
 #define SCE_ASN1_DESCRIPTOR 8
 #define SCE_ASN1_TYPE 9
 #define SCE_ASN1_OPERATOR 10
+#define SCE_VHDL_DEFAULT 0
+#define SCE_VHDL_COMMENT 1
+#define SCE_VHDL_COMMENTLINEBANG 2
+#define SCE_VHDL_NUMBER 3
+#define SCE_VHDL_STRING 4
+#define SCE_VHDL_OPERATOR 5
+#define SCE_VHDL_IDENTIFIER 6
+#define SCE_VHDL_STRINGEOL 7
+#define SCE_VHDL_KEYWORD 8
+#define SCE_VHDL_STDOPERATOR 9
+#define SCE_VHDL_ATTRIBUTE 10
+#define SCE_VHDL_STDFUNCTION 11
+#define SCE_VHDL_STDPACKAGE 12
+#define SCE_VHDL_STDTYPE 13
+#define SCE_VHDL_USERWORD 14
 //--Autogenerated -- end of section automatically generated from Scintilla.iface
 
 #endif
diff --git a/include/Scintilla.iface b/include/Scintilla.iface
index a31148270..d79f97a64 100644
--- a/include/Scintilla.iface
+++ b/include/Scintilla.iface
@@ -1750,6 +1750,7 @@ val SCLEX_AU3=60
 val SCLEX_APDL=61
 val SCLEX_BASH=62
 val SCLEX_ASN1=63
+val SCLEX_VHDL=64
 
 # When a lexer specifies its language as SCLEX_AUTOMATIC it receives a
 # value assigned in sequence from SCLEX_AUTOMATIC+1.
@@ -2560,6 +2561,23 @@ val SCE_ASN1_ATTRIBUTE=7
 val SCE_ASN1_DESCRIPTOR=8
 val SCE_ASN1_TYPE=9
 val SCE_ASN1_OPERATOR=10
+# Lexical states for SCLEX_VHDL
+lex VHDL=SCLEX_VHDL SCE_VHDL_
+val SCE_VHDL_DEFAULT=0
+val SCE_VHDL_COMMENT=1
+val SCE_VHDL_COMMENTLINEBANG=2
+val SCE_VHDL_NUMBER=3
+val SCE_VHDL_STRING=4
+val SCE_VHDL_OPERATOR=5
+val SCE_VHDL_IDENTIFIER=6
+val SCE_VHDL_STRINGEOL=7
+val SCE_VHDL_KEYWORD=8
+val SCE_VHDL_STDOPERATOR=9
+val SCE_VHDL_ATTRIBUTE=10
+val SCE_VHDL_STDFUNCTION=11
+val SCE_VHDL_STDPACKAGE=12
+val SCE_VHDL_STDTYPE=13
+val SCE_VHDL_USERWORD=14
 
 # Events
 
diff --git a/src/KeyWords.cxx b/src/KeyWords.cxx
index c137c1bcb..66e82094c 100644
--- a/src/KeyWords.cxx
+++ b/src/KeyWords.cxx
@@ -190,6 +190,7 @@ int Scintilla_LinkLexers() {
 	LINK_LEXER(lmVB);
 	LINK_LEXER(lmVBScript);
 	LINK_LEXER(lmVerilog);
+	LINK_LEXER(lmVHDL);
 	LINK_LEXER(lmYAML);
 
 //--Autogenerated -- end of automatically generated section