aboutsummaryrefslogtreecommitdiffhomepage
diff options
context:
space:
mode:
authorssteele <devnull@localhost>2004-02-16 11:31:32 +0000
committerssteele <devnull@localhost>2004-02-16 11:31:32 +0000
commitc906dfb820a899ec5fd0f0b6498eacd5a68218b2 (patch)
tree19c877762224e497e30eefcde69bb24de8e35727
parent34ecc6f11a7d9c6cd2004867980e611e31930791 (diff)
downloadscintilla-mirror-c906dfb820a899ec5fd0f0b6498eacd5a68218b2.tar.gz
Added MSSQL and Verilog lexers.
-rw-r--r--vcbuild/SciLexer.dsp8
1 files changed, 8 insertions, 0 deletions
diff --git a/vcbuild/SciLexer.dsp b/vcbuild/SciLexer.dsp
index 1015bd646..d32f82618 100644
--- a/vcbuild/SciLexer.dsp
+++ b/vcbuild/SciLexer.dsp
@@ -230,6 +230,10 @@ SOURCE=..\src\LexMPT.cxx
# End Source File
# Begin Source File
+SOURCE=..\src\LexMSSQL.cxx
+# End Source File
+# Begin Source File
+
SOURCE=..\src\LexNsis.cxx
# End Source File
# Begin Source File
@@ -282,6 +286,10 @@ SOURCE=..\src\LexVB.cxx
# End Source File
# Begin Source File
+SOURCE=..\src\LexVerilog.cxx
+# End Source File
+# Begin Source File
+
SOURCE=..\src\LexYAML.cxx
# End Source File
# Begin Source File