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| author | Joe Mueller <devnull@localhost> | 2015-03-10 15:14:14 -0700 |
|---|---|---|
| committer | Joe Mueller <devnull@localhost> | 2015-03-10 15:14:14 -0700 |
| commit | fe85d455e4ee2edaf55ac42077e7d9642fb9688e (patch) | |
| tree | f5378ad63f564c6c15a65be83c47973ebd9ae2b2 | |
| parent | 4a976d45762201f2dbe979a2df648e97dc7d0924 (diff) | |
| download | scintilla-mirror-fe85d455e4ee2edaf55ac42077e7d9642fb9688e.tar.gz | |
fix problem where preprocessor fold code would incorrectly match `endcelldefine with `if
| -rw-r--r-- | lexers/LexVerilog.cxx | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lexers/LexVerilog.cxx b/lexers/LexVerilog.cxx index 2a53a1846..1e45a06bc 100644 --- a/lexers/LexVerilog.cxx +++ b/lexers/LexVerilog.cxx @@ -853,7 +853,7 @@ void SCI_METHOD LexerVerilog::Fold(unsigned int startPos, int length, int initSt } if (styler.Match(j, "if")) { levelNext++; - } else if (styler.Match(j, "end")) { + } else if (styler.Match(j, "endif")) { levelNext--; } } |