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authornyamatongwe <devnull@localhost>2004-01-20 10:39:33 +0000
committernyamatongwe <devnull@localhost>2004-01-20 10:39:33 +0000
commit90bf78ccc9dac99db85fe79218ec2ecd4b86c990 (patch)
tree72c255011a8c7c53f01ae3385454d911e8e8c0da /win32/scintilla_vc6.mak
parent0134525521731911f9e51bdc4be12b6a6f52c510 (diff)
downloadscintilla-mirror-90bf78ccc9dac99db85fe79218ec2ecd4b86c990.tar.gz
Support from Avi Yegudin for Verilog.
Diffstat (limited to 'win32/scintilla_vc6.mak')
-rw-r--r--win32/scintilla_vc6.mak3
1 files changed, 3 insertions, 0 deletions
diff --git a/win32/scintilla_vc6.mak b/win32/scintilla_vc6.mak
index 53ad2fd1d..176e089f6 100644
--- a/win32/scintilla_vc6.mak
+++ b/win32/scintilla_vc6.mak
@@ -148,6 +148,7 @@ LEXOBJS=\
$(DIR_O)\LexSQL.obj \
$(DIR_O)\LexTeX.obj \
$(DIR_O)\LexVB.obj \
+ $(DIR_O)\LexVerilog.obj \
$(DIR_O)\LexYAML.obj \
#--Autogenerated -- end of automatically generated section
@@ -332,6 +333,8 @@ $(DIR_O)\LexTeX.obj: ..\src\LexTeX.cxx $(LEX_HEADERS)
$(DIR_O)\LexVB.obj: ..\src\LexVB.cxx $(LEX_HEADERS)
+$(DIR_O)\LexVerilog.obj: ..\src\LexVerilog.cxx $(LEX_HEADERS)
+
$(DIR_O)\LexYAML.obj: ..\src\LexYAML.cxx $(LEX_HEADERS)