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| author | ssteele <devnull@localhost> | 2004-10-25 09:10:49 +0000 |
|---|---|---|
| committer | ssteele <devnull@localhost> | 2004-10-25 09:10:49 +0000 |
| commit | 75882b9ddcae190a519aeb8fa390e3289bae8664 (patch) | |
| tree | 428746e66b19ff5f0fabad4c73fc5bbcd5b8390e | |
| parent | 9005cba353b70d7bcbb963703e569a12b2c2fa98 (diff) | |
| download | scintilla-mirror-75882b9ddcae190a519aeb8fa390e3289bae8664.tar.gz | |
Added missing lexers.
| -rw-r--r-- | vcbuild/SciLexer.dsp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/vcbuild/SciLexer.dsp b/vcbuild/SciLexer.dsp index 0a88f70a2..e41464cbd 100644 --- a/vcbuild/SciLexer.dsp +++ b/vcbuild/SciLexer.dsp @@ -150,6 +150,10 @@ SOURCE=..\src\LexAsm.cxx # End Source File # Begin Source File +SOURCE=..\src\LexAsn1.cxx +# End Source File +# Begin Source File + SOURCE=..\src\LexAU3.cxx # End Source File # Begin Source File @@ -314,6 +318,10 @@ SOURCE=..\src\LexVerilog.cxx # End Source File # Begin Source File +SOURCE=..\src\LexVHDL.cxx +# End Source File +# Begin Source File + SOURCE=..\src\LexYAML.cxx # End Source File # Begin Source File |