diff options
| -rw-r--r-- | vcbuild/SciLexer.dsp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/vcbuild/SciLexer.dsp b/vcbuild/SciLexer.dsp index 0a88f70a2..e41464cbd 100644 --- a/vcbuild/SciLexer.dsp +++ b/vcbuild/SciLexer.dsp @@ -150,6 +150,10 @@ SOURCE=..\src\LexAsm.cxx # End Source File # Begin Source File +SOURCE=..\src\LexAsn1.cxx +# End Source File +# Begin Source File + SOURCE=..\src\LexAU3.cxx # End Source File # Begin Source File @@ -314,6 +318,10 @@ SOURCE=..\src\LexVerilog.cxx # End Source File # Begin Source File +SOURCE=..\src\LexVHDL.cxx +# End Source File +# Begin Source File + SOURCE=..\src\LexYAML.cxx # End Source File # Begin Source File |