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-rw-r--r--win32/scintilla.mak3
-rw-r--r--win32/scintilla_vc6.mak3
2 files changed, 6 insertions, 0 deletions
diff --git a/win32/scintilla.mak b/win32/scintilla.mak
index 79f4dff32..b4ca7204a 100644
--- a/win32/scintilla.mak
+++ b/win32/scintilla.mak
@@ -167,6 +167,7 @@ LEXOBJS=\
$(DIR_O)\LexVB.obj \
$(DIR_O)\LexVerilog.obj \
$(DIR_O)\LexVHDL.obj \
+ $(DIR_O)\LexVisualProlog.obj \
$(DIR_O)\LexYAML.obj \
#--Autogenerated -- end of automatically generated section
@@ -454,6 +455,8 @@ $(DIR_O)\LexVerilog.obj: ..\lexers\LexVerilog.cxx $(LEX_HEADERS)
$(DIR_O)\LexVHDL.obj: ..\lexers\LexVHDL.cxx $(LEX_HEADERS)
+$(DIR_O)\LexVisualProlog.obj: ..\lexers\LexVisualProlog.cxx $(LEX_HEADERS)
+
$(DIR_O)\LexYAML.obj: ..\lexers\LexYAML.cxx $(LEX_HEADERS)
diff --git a/win32/scintilla_vc6.mak b/win32/scintilla_vc6.mak
index df1c13aff..2f900ab01 100644
--- a/win32/scintilla_vc6.mak
+++ b/win32/scintilla_vc6.mak
@@ -169,6 +169,7 @@ LEXOBJS=\
$(DIR_O)\LexVB.obj \
$(DIR_O)\LexVerilog.obj \
$(DIR_O)\LexVHDL.obj \
+ $(DIR_O)\LexVisualProlog.obj \
$(DIR_O)\LexYAML.obj \
#--Autogenerated -- end of automatically generated section
@@ -453,6 +454,8 @@ $(DIR_O)\LexVerilog.obj: ..\lexers\LexVerilog.cxx $(LEX_HEADERS)
$(DIR_O)\LexVHDL.obj: ..\lexers\LexVHDL.cxx $(LEX_HEADERS)
+$(DIR_O)\LexVisualProlog.obj: ..\lexers\LexVisualProlog.cxx $(LEX_HEADERS)
+
$(DIR_O)\LexYAML.obj: ..\lexers\LexYAML.cxx $(LEX_HEADERS)